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Integrated Circuit Systems, Inc.
ICS9248-92
TM
Mobile Pentium II System Clock Chip
Recommended Application: The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements. General Description: Features include two strong CPU, seven PCI and eight SDRAM clocks. Three reference outputs are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output (ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs). PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will stop PCICLK (0:5) clocks PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 505% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9248-92 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
Features
* * * * * * * * * * Generates system clocks for CPU, SDRAM, PCI, plus 14.318 MHz REF(0:2), USB, Plus Super I/O I2C serial configuration interface provides output clock disabling and other functions MODE input pin selects optional power management input control pins Two fixed outputs separately selectable as 24 or 48MHz 2.5V outputs: CPU 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz No power supply sequence requirements Uses external 14.318MHz crystal 48 pin 240 mil TSSOP package Output enable register for serial port control: 1 = enable 0 = disable
Pin Configuration Block Diagram
48-Pin TSSOP 240 mil Package
Functionality
Crystal (X1, X2) = 14.31818 MHz
SEL 100/66# 0
Pentium is a trademark on Intel Corporation. 9248-92 Rev E 02/21/01
CPUCLK (MHz) 66.6 100
PCICLK (MHz) 33.3 33.3
1
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-92
Pin Descriptions
PIN NUMBER 45, 1, 2 3, 10, 17, 24, 31, 37, 43 4 5 6 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25 26 27 28, 34 40 42, 41 36, 35, 33, 32, 30, 29 38 39 44 48, 46 PIN NAME REF [2:0] GND X1 X2 MODE VDDPCI PCICLK_F PCICLK [0:5] SEL100/66# SDATA SCLK VDD48 48/24MHzA 48/24MHzB VDDCOR SDRAM7 PCI_STOP# SDRAM6 CPU_STOP# VDDSDR VDDLCPU CPUCLK [0:1] SDRAM [0:5] FB BUF_IN PWR_DWN# VDDREF TYPE OUT PWR IN OUT IN PWR OUT OUT IN IN IN PWR OUT OUT PWR OUT IN OUT IN PWR PWR OUT OUT OUT IN IN PWR DESCRIPTION Reference clock Output Ground (common) Crystal or reference input, has internal crystal load cap Crystal output, has internal load cap and feedback resistor to X1 Input function selection (see table page 3) Supply for PCICLK_F, PCICLK [0:5], nominal 3.3V Free running PCI clock, not affected by PCI_STOP# PCI clocks Selects 66.6MHz or 100MHz for SDRAM and CPU (see tables page 1, 3) I2C data input I2C clock input Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V 48/24MHz driver output for USB or Super I/O 48/24MHz driver output for USB or Super I/O Supply for PLL core, nominal 3.3V SDRAM clock output, fanout buffer output from BUF_IN pin Halts PCI Bus [0:5] at logic "0" level when low SDRAM clock output, fanout buffer output from BUF_IN pin Halts CPU clocks at logic "0" level when low Supply for SDRAM [0:5], SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, nominal 3.3V Supply for CPUCLK [0:1] 2.5V nominal CPUCLK clock output, powered by VDDL2 SDRAM clock outputs, fanout buffer outputs from BUF_IN pin Feedback out Input for SDRAM buffers When driven active (low) powers down the device into low power state. Internal clocks are disabled, VCO and crystal OSC are stopped. Supply for REF [0:2], X1, X2, nominal 3.3V
Power Groups
VDDCOR = Supply for PLL core VDDREF = REF [0:2], X1, X2 VDDPCI = PCICLK_F, PCICLK [0:5] VDDSDR = SDRAM [0:7] VDD48 = 48/24MHzA, 48/24MHz VDDLCPU = CPUCLK [0:1] 2
ICS9248-92
Power-On Conditions
SEL 100/66.6# 1 MODE 1 PIN # 41, 42 16, 14, 13, 12, 11, 9, 8 41, 42 16, 14, 13, 12, 11, 9, 8 26 27 1 0 8 41, 42 16, 14, 13, 12, 11, 9 26 27 0 0 8 41, 42 16, 14, 13, 12, 11, 9 DESCRIPTION CPUCLKs PCICLKs CPUCLKs PCICLKs PCI_STOP# CPU_STOP# PCICLK_F CPUCLKs PCICLKs PCI_STOP# CPU_STOP# PCICLK_F CPUCLKs PCICLKs FUNCTION 100 MHz - w/serial config enable/disable 33.3 MHz - w/serial config enable/disable 66.6 MHz - w/serial config enable/disable 33.3 MHz - w/serial config enable/disable Power Management, PCI [0:5] Clocks Stopped when low Power Management, CPU [0:5] Clocks Stopped when low 33.3 MHz - PCI Clock Free running 100 MHz - CPU Clocks w/external Stop Control and serial config individual enable/disable. 33.3 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable. Power Management, PCI [0:5] Clocks Stopped when low Power Management, CPU [0:5] Clocks Stopped when low 33.3 MHz - PCI Clock Free running for Power Management 66.6 MHz - CPU Clocks w/external Stop control and serial config individual enable/disable. 33.3 MHz - PCI Clocks w/external Stop control and serial config individual enable/disable.
0
1
Example: a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively. b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and "on" condition. The frequencies that are then produced are on the MODE pin as shown in the table below.
CLOCK REF (0:2) 48/24 MHz
D E FAU LT C O N D I T I O N AT P OW E R - U P 14.31818 MHz 48 MHz
3
ICS9248-92
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-92
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0) (default on Bits 3, 2 = 1) Note: PWD = Power-Up Default
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 23 22 PIN# DESCRIPTION R e s e r ve d R e s e r ve d In Spread Spectrum, Controls type ( 0 = c e n t e r e d , 1 = d ow n s p r e a d ) In Spread Spectrum, Controls Spreading (0=0.5% 1=0.25%) 4 8 / 2 4 M H z ( F r e q u e n cy S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z 4 8 / 2 4 M H z ( F r e q u e n cy S e l e c t ) 1 = 4 8 M H z , 0 = 2 4 M H z Bit0 Bit1 1 - Tr i - S t a t e 1 0 - Spread Spectrum Enable 1 1 - Te s t m o d e 0 0 - Normal operation 0 PWD 0 0 1 0 1 1
-
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Select Functions
Functionality Tristate Testmode CPU HI - Z TCLK/2
1
PCI, PCI_F HI - Z TCLK/4
1
SDRAM HI - Z TCLK/2
1
REF HI - Z TCLK
1
24 MHz Selection HI - Z TCLK/4
1
48 MHz Selection HI - Z TCLK/21
Notes: 1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
5
ICS9248-92
Byte 1: CPU, 24/48 MHz Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 23 22 41 42 PWD 1 1 1 1 1 1 1 1 DESCRIPTION 48/24 MHz (Act/Inact) 48/24 MHz (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCICLK Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 8 16 14 13 12 11 9 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d PCICLK_F (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 26 27 29 30 32 33 35 36 PWD 1 1 1 1 1 1 1 1 DESCRIPTION SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1(Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 5: Peripheral Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 45 1 2 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d REF2 (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact)
Byte 6: Optional Register for Future
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low PWD = Power-Up Default
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
Note: PWD = Power-Up Default
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ICS9248-92
Power Management
Clock Enable Configuration
Other Clocks, SDRAM, REF, 48/24 MHz A 48/24 MHz B Stopped Running Running Running Running
C P U _ S TO P #
P C I _ S TO P #
P W R _ DW N #
CPUCLK
PCICLK
Crystal
VCOs
X 0 0 1 1
X 0 1 0 1
0 1 1 1 1
L ow Low Low 100/66.6 MHz 100/66.6 MHz
L ow Low 33.3 MHz Low 33.3 MHz
O ff Running Running Running Running
O ff Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-92 Power Management Requirements
SIGNAL C P U _ S TO P # P C I _ S TO P # PWR_DWN# SIGNAL STATE 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 L a t e n cy No. of rising edges of free running PCICLK 1 1 1 1 3mS 2max
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only. The REF will be stopped independant of these.
7
ICS9248-92
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-92. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-92. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-92. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-92 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
8
ICS9248-92
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9248-92 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don't care signals during the power down operations.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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ICS9248-92
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% VDDL = 2.5V +/-5% (unless otherwise stated) PARAM ETER Input High Voltage Input Low Voltage Supply Current Input frequency Input Capacitance 1 Transition Time 1 Clk Stabilization 1 Skew 1 SYMBOL VIH VIL IDD IDDL2.5 Fi C IN C INX T tran s T STAB T CPU-PCI CONDITIONS M IN 2 VSS -0.3 M AX UNITS VDD+0.3 V 0.8 V 77 180 mA 2.8 25 mA 14.318 M Hz 5 pF 36 45 ps 1.5 1.5 2.2 3 3 4.0 ms ms ns TYP
C L = 0 pF; Select @ 66M VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From V DD = 3.3 V to 1% target Freq.
27
1
VTP CI = 1.5 V; VTCP U = 1.25 V Guarenteed by design, not 100% tested in production.
10
ICS9248-92
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 20 pF (unless otherwise stated) PARAMETER Period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL period(norm) VOH2B VOL2B IOH2B IOL2B t r2B1 t f2B
1 1
CONDITIONS VT = 1.25 V; 100MHz IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V
MIN 10 1.8
TYP 10 2.3 0.31
MAX 10.5 0.4 -27 1.6
27 1 45 50 30 186 1.6 55 95 250
UNITS ns V V mA mA ns ns % ps ps
d t2B
t sk2B1 t cyc-cyc
1
VT = 1.25 V VT = 1.25 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz,24MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, Absolute1 Jitter, Absolute1
1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tjabs5 tjabs5
CONDITIONS IOH = -14 mA IOL = 6.0 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, REF VT = 1.5 V, 48 MHz
MIN 2
TYP 3.21 0.21
29 1 1 45 2.5 2.5 52 385 469
MAX UNITS V 0.4 V -23 mA mA 4 4 55 800 800 ns ns % ps ps
Guaranteed by design, not 100% tested in production.
11
ICS9248-92
Electrical Characteristics - PCICLK
T A = 0 - 70 C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 30 pF (unless otherwise stated) PA RA M ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time Skew
1 1 1 1 1
SYM BOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjabs1 t jcy c-cyc1
CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
M IN 2.1
TYP 3.3 0.17
30 0.5 0.5 45 -250 227 1.6 1.8 50 222
M A X UNITS V 0.4 V -24 mA mA 2 2 55 500 250 500 ns ns % ps ps ps
Duty Cycle
Jitter, A bs olute Jitter, Cycle-to-cycle 1
1
Guaranteed by des ign, not 100% tes ted in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tp1
CONDITIONS IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.2
TYP 3.18 0.35 -74 1.54 1.51 51 200 3.5
54 0.5 0.5 45 1
MAX UNITS V 0.4 V -46 mA mA 1.6 1.6 55 250 5 ns ns % ps ns
Duty Cycle
Skew Propagation Delay1
1
Guaranteed by design, not 100% tested in production.
12
ICS9248-92
General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Ferrite Bead VDD
C2 22F/20V Tantalum
C2 22F/20V Tantalum
Ferrite Bead VDD
1
3.3V Power Route
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3.3V Power Route 2.5V Power Route C3 C4 1 Clock Load
2 3
C1
Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C1
2
Component Values: C1 : Crystal load values determined by user C2 : 22 F/20V/D case/Tantalum AVX TAJD226M020R C3 : 15pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01 F ceramic
19 20 21 22 23 24
= Routed Power
Connections to VDD:
= Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
13
ICS9248-92
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
N 48
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
7/6/00 Rev B
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS9248yG-92
Example:
ICS XXXX y G - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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